The present invention relates in general to programmable logic circuits, and in particular to a circuit and methodology that allow the user to observe the state of internal nodes within the programmable logic circuit.
A growing trend in the field of electronic circuits and systems design is the use of prototyping or emulation systems that are built with programmable logic devices (PLDs). Such emulation systems help in debugging complex designs with quick turn-around which ensure successful time-to-market for the final product. Programmable logic devices, including programmable logic arrays (PLAs) and field programmable gate arrays (FPGAs) are particularly suited for such debug systems since they provide the flexibility required by design adjustments resulting from design errors or enhancements. Furthermore, such hardware prototyping solutions are often fast enough to operate in the context of the rest of the system. This gives the system designers a high degree of confidence.
A drawback of existing PLD-based emulation or prototyping systems, however, is that the internal state of the programmable logic devices are inaccessible and buried inside the device. This limits the troubleshooting and debugging capabilities of the system. Software based emulation systems provide for complete observability of all nodes within the system, but at the cost of running from 100 to 1 million times slower than the rest of the system.
There is therefore a need for programmable logic devices that can operate at full system speed while simultaneously providing access to observe the state of internal nodes of the device.